Reconfigurable PLL for Digital System

Low power and high throughput digital systems are required in the number of applications such as Computer Graphics, Virtual Reality, System Control, Image Processing, and Digital Signal Processing etc. The various approaches suggested by researchers for power efficient high throughput architectures include pipelining, parallelism, retiming, folding-unfolding, using multiprocessor environment etc. An approach to dynamically derive different on chip clock signals to drive various sub blocks depending upon their time complexity is proposed in this paper. This approach is expected to reduce power dissipation besides increasing the throughput of the digital system. A phase locked loop circuit which is generally used to generate the frequencies which are integral multiple of input signal frequency is proposed to be implemented in a reconfigurable aspect to derive the required clock signals. In this paper we have proposed reconfigurable PLL, which generates another clock signal in run time, as per the requirement of the processing blocks in the system. Keyword: power efficiency, high throughput, reconfigurable PLL